1. Field of the Invention
The present invention relates to an insulated gate semiconductor device having trench.cndot.gate and a manufacturing method thereof.
2. Description of the Background Art
The insulated gate semiconductor device is a semiconductor device having the structure in which p-type and n-type semiconductor layers are alternately joined, main electrodes through which main current flows are electrically connected to the semiconductor layers on both ends, and a gate electrode for forming a channel by applying the electric field is connected to at least one of the semiconductor layers with an insulating film interposed therebetween. In this insulated gate semiconductor device, the current flowing between the two main electrodes, i.e., the main current, is controlled by the voltage applied to the gate electrode. Typical examples thereof include the MOS transistors and the insulated gate bipolar transistors (simply referred to as IGBT).
The IGBTs for electric power generally have the structure in which a large number of IGBT elements (referred to as unit cells, hereinafter) are connected in parallel. It is the same in the MOS transistors for electric power, too. Especially, the insulated gate semiconductor devices having trench.cndot.gate, that is, the devices having the structure in which the gate electrode is buried in the trench formed in the upper surface of the semiconductor substrate have attracted special interest as excellent devices having such advantages as being capable of enhancing the integration degree because of easy miniaturization and simple producing processes. Two examples of the conventional insulated gate semiconductor devices having the trench.cndot.gate will now be described below.
&lt;First Conventional Example&gt;
First, the MOS transistor having trench gate (referred to as UMOS hereinafter) disclosed in U.S. Pat. No. 4,767,722 is considered. FIG. 40 is a front section view of this device. A section of one unit cell is shown in FIG. 40. In this UMOS 40, an N.sup.- -type semiconductor layer 4 containing N-type impurity of a low concentration is formed on a semiconductor substrate constituting an N.sup.+ -type semiconductor layer 1 containing N-type impurity of a high concentration, and a P base layer 5 is formed by diffusing P-type impurity on the N.sup.- semiconductor layer 4. Furthermore, on the upper main surface of the P base layer 5, an N.sup.+ emitter layer 6 is selectively formed by selectively diffusing N-type impurity of a high concentration. These four semiconductor layers constitute a flat board like semiconductor base body 20. A trench 7 is formed in the upper main surface of the semiconductor base body 20 from the exposed part of the N.sup.+ emitter layer 6 toward the deeper portion. This trench 7 passes through the N.sup.+ emitter layer 6 and the P base layer 5 to reach the N.sup.- semiconductor layer 4. Accordingly, the side surface of the trench 7 is adjacent to the N.sup.+ emitter layer 6, the P base layer 5 and the upper surface portion of the N.sup.- semiconductor layer 4.
A gate insulating film 9 is formed on the inner wall surface of the trench 7, and a gate electrode 10 composed of polysilicon is buried inside the gate insulating film 9. Accordingly, the gate electrode 10 faces the N.sup.+ emitter layer 6, the P base layer 5 and the upper surface portion of the N.sup.- semiconductor layer 4 with the gate insulating film 9 interposed therebetween. The voltage is applied to the gate electrode 10 and then an N channel is formed in the P base layer 5. That is, the region of the P base layer 5 facing the gate electrode 10 serves as a channel region 8. A drain electrode 13 is formed on the lower main surface of the semiconductor base body 20, i.e., on the lower main surface of the N.sup.+ semiconductor layer 1. A source electrode 12 is formed over part of the exposed N.sup.+ emitter layer 6 and the exposed P base layer 5 in the upper main surface of the semiconductor base body 20.
FIG. 41 is a plan view of the UMOS 40 shown in FIG. 40. The upper main surface of the UMOS 40 with the source electrode 12 removed therefrom, i.e., the upper main surface of the semiconductor base body 20 is shown in FIG. 41. As shown in FIG. 41, the gate electrode 10 is formed in a lattice-like form, and the N.sup.+ emitter layer 6 is exposed in the upper main surface of the semiconductor base body 20 in the form like rectangular rings adjacent to the rectangular gate electrode 10. Further, the P base layer 5 is exposed on the upper main surface of the semiconductor base body 20 in the rectangular areas surrounded by the ring-like N.sup.+ emitter layer 6. In FIG. 41, the outlines of the regions in which the source electrode 12 is in contact with the upper main surface of the semiconductor base body 20 are represented by the dotted lines. That is, the source electrode 12 is electrically connected to the entire surface of the P base layer 5 exposed in the rectangular regions and part of the N.sup.+ emitter layer 6 adjacent to the periphery thereof.
When using this UMOS 40, the external power source is first connected to apply a drain voltage V.sub.DS in the positive direction between the drain electrode 13 and the source electrode 12. In this condition, a gate voltage V.sub.GS exceeding a predetermined gate threshold voltage V.sub.GS(th) is applied in the positive direction between the gate electrode 10 and the source electrode 12 (i.e., the gate is turned on), and then the P-type channel region 8 which is a part of the P-type P base layer 5 is inverted to the N-type to form an N-type channel in the channel region 8. This channel implements a conductive state between the p base layer 5 and the N.sup.- semiconductor layer 4. As a result, the main current flows from the drain electrode 13 to the source electrode 12. That is, the UMOS 40 goes into the conductive state. The resistance between the drain electrode 13 and the source electrode 12 at this time is called ON resistance R.sub.ON. It is desirable that the ON resistance R.sub.ON is as low as possible to decrease the loss when the UMOS 40 becomes conductive.
Next, when the gate voltage V.sub.GS is returned to a value of zero or minus (backward bias), (that is, the gate is turned off), the channel formed in the channel region 8 disappears and the channel region 8 returns to the original P-type conductivity form. As a result, it is cut off between the P base layer 5 and N.sup.- semiconductor layer 4, so that the main current does not flow. That is to say, the UMOS 40 becomes non-conductive.
&lt;Second Conventional Example&gt;
Next, another example of conventional device is considered. FIG. 42 is a fragmentary cross-section perspective view of the IGBT (referred to as UMOS-IGBT hereinafter) having trench gate disclosed in U.S. Pat. No. 4,994,871. Three unit cells are shown in FIG. 42. In this UMOS-IGBT 80, an N.sup.+ buffer layer 63 containing N-type impurity of a high concentration is formed on a semiconductor substrate constituting a P.sup.+ collector layer 62 containing P-type impurity of a high concentration, and an N.sup.- semiconductor layer 64 containing N-type impurity of a low concentration is formed on the N.sup.+ buffer layer 63. On the N.sup.- semiconductor layer 64, a P base layer 65 is formed by diffusing P-type impurity, and on the upper main surface of the P base layer 65, an N.sup.+ emitter layer 66 is formed in a stripe form by selectively diffusing N-type impurity of a high concentration. That is, the N.sup.+ emitter layer 66 and the P base layer 65 are exposed on the upper main surface of the semiconductor base body 60 alternately in the stripe form. These five semiconductor layers form the flat board like semiconductor base body 60.
Trenches 67 are formed on the upper main surface of this semiconductor base body 60. The trenches 67 are formed in the stripe shape, and are arranged in the direction perpendicular to the stripe-like N.sup.+ emitter layer 66. The trench 67 is formed extending from the upper main surface of the semiconductor base body 60 through the N.sup.+ emitter layer 66 and the P base layer 65 to reach the N.sup.- semiconductor layer 64. A gate insulating film 69 is formed on the inner wall surface of the trench 67, and a gate electrode 70 is buried inside of it. The region of the P base layer 65 facing the gate electrode 70 and is interposed between the N.sup.+ emitter layer 66 and the N.sup.- semiconductor layer 64 serves as a channel region 68.
A collector electrode 73 is formed on the lower main surface of the semiconductor base body 60, that is, on the lower main surface of the P.sup.+ collector layer 62. An emitter electrode 72 is formed in the portion in which the N.sup.+ emitter layer 66 is exposed and the portion in which the P base layer 65 is exposed on the upper main surface of the semiconductor base body 60.
When using this UMOS-IGBT 80, first, an external power source is connected to apply a collector voltage V.sub.CE in the positive direction between the collector electrode 73 and the emitter electrode 72. In this condition, a gate voltage V.sub.GE exceeding a predetermined gate threshold voltage V.sub.GE(tb) is applied in the positive direction between the gate electrode 70 and the emitter electrode 72 (that is, the gate is turned on), and then the P-type channel region 68 is inverted to the N-type to form an N-type channel in the channel region 68. Electrons are injected from the emitter electrode 72 via the N.sup.+ emitter layer 66 to the N.sup.- semiconductor layer 64. These injected electrons cause forward bias between the P.sup.+ collector layer 62 and the N.sup.- semiconductor layer 64 (including the N.sup.+ buffer layer 63), and holes are injected from the P.sup.+ collector layer 62 to the N.sup.- semiconductor layer 64. As a result, the resistance of the N.sup.- semiconductor layer 64 largely decreases so that large main current flows from the collector electrode 73 to the emitter electrode 72. The voltage produced between the collector electrode 73 and the emitter electrode 72 at this time is called ON voltage V.sub.CE(sat). The ON voltage V.sub.CE(sat) is converted into resistance to be the ON resistance R.sub.ON described above. It is desirable that the ON voltage V.sub.CE(sat) or the ON resistance R.sub.ON is as low as possible to decrease the loss when the UMOS-IGBT 80 becomes conductive. As described above, the IGBT is formed so that the injection of holes from the P.sup.+ collector layer 62 causes the resistance of the N.sup.- semiconductor layer 64 to be decreased.
Next, when the gate voltage V.sub.GE is returned to a value of zero or minus (backward bias), (that is, the gate is turned off), the channel formed in the channel region 68 disappears and the channel region 68 returns to the original P-type conductivity form. As a result, the injection of electrons from the emitter electrode 72 stops and then the injection of holes from the P.sup.+ collector layer 62 also stops. After that, the electrons and holes remaining in the N.sup.- semiconductor layer 64 (and the N.sup.+ buffer layer 63) are recovered to the collector electrode 73 and the emitter electrode 72, respectively, or they are bonded again. At this time, since the holes decrease slower than the electrons decrease, the current flowing until the holes are recovered to the emitter electrode 72 causes so-called "tail current". In the UMOS-IGBT, the injection of holes from the emitter electrode 72 has an important role, which is different from the UMOS.
Generally, it is said that making the unit cells smaller, that is, the miniaturization is effective to decrease the ON voltage V.sub.CE(sat) in the UMOS or UMOS-IGBT. In the first conventional example, however, the ring-like exposure surface of the N.sup.+ emitter layer 6 must have a certain or larger width to certainly realize the electric contact between the source electrode 12 and the N.sup.+ emitter layer 6. This is due to the fact that redundant design is required because there is a certain limit in accurately positioning the contact plane of the source electrode 12 and the semiconductor base body 20 so as to cover the inner portion of the ring-like N.sup.+ emitter layer 6.
In the second conventional example, since the stripe-like N.sup.+ emitter layer 66 and the stripe-like gate electrode 70 are arranged perpendicularly, the electric contact between the N.sup.+ emitter layer 66, the P base layer 65 and the emitter electrode 72 is ensured even if the position of the contact plane of the emitter electrode 72 and the upper main surface of the semiconductor base body 60 is shifted. Accordingly, the redundant design required in the first conventional example is not needed, which is therefore advantageous in that the miniaturization is easy. In the second conventional example, however, since the stripe-like N.sup.+ emitter layer 66 is perpendicular to the gate electrode 70 in contrast to the first conventional example in which the N.sup.+ emitter layer 6 is formed along the gate electrode 10, the N.sup.+ emitter layer 66 does not face to the gate electrode 70 in the portion in which the P base layer 65 is exposed on the upper main surface of the semiconductor base body 60. That is, the channel region 68 is not continuously formed along the gate electrode 70 but it discontinues at the portion where the P base layer 65 is exposed. Accordingly, in the second conventional example, the width of the channel region 68 is shorter as compared with the first conventional example. This works to increase the ON voltage V.sub.CE(sat). That is, in the second conventional example, though the miniaturization is realized, there is a problem that it does not effectively contribute to decrease the ON voltage V.sub.CE(sat).
Also, both of the first and second conventional examples involve a problem that the ON voltage V.sub.CE(sat) increases if the unit cells are miniaturized over a certain level. This is caused because the contact area (area in contact) between the N.sup.+ emitter layer 6 (N.sup.+ emitter layer 66) and the source electrode 12 (emitter electrode 72) which is a main path of the main current becomes excessively small with miniaturization, resulting in an increase in the contact resistance therebetween. The increase of the contact resistance causes the ON voltage V.sub.CE(sat) (ON resistance R.sub.ON) to increase.
Furthermore, with the miniaturization, the contact area between the P base layer 5 (P base layer 65) and the source electrode 12 (emitter electrode 72) also becomes too small. This induces conduction of a parasitic transistor in both the UMOS-IGBT and the UMOS. As shown in FIG. 42, a bipolar transistor is parasitically formed with the N.sup.+ emitter layer 66, the P base layer 65 and the N.sup.- semiconductor layer 64 in the UMOS-IGBT 80. This parasitic transistor becomes conductive when the potential of the N.sup.- semiconductor layer 64 exceeds built-in potential between the P base layer 65 and the N.sup.+ emitter layer 66. This parasitic transistor parasitically forms a thyristor together with the original transistor existing in the UMOS-IGBT 80. Therefore, the parasitic thyristor is triggered if the parasitic transistor once becomes conductive. As a result, in the UMOS-IGBT 80, the main current can not be controlled by the gate voltage V.sub.GE applied to the gate electrode 70 any more. That is to say, the main current continuously flows irrespective of the gate voltage V.sub.GE. Accordingly, the parasitic transistor becomes conductive to result in breakdown of the UMOS-IGBT 80. This can be generally said for the IGBTs.
Moreover, the same can be said for the UMOS. As shown in FIG. 40, a bipolar transistor is parasitically formed with the N.sup.+ emitter layer 6, the P base layer 5 and the N.sup.- semiconductor layer 4 in the UMOS 40. This parasitic transistor becomes conductive when the potential of the N.sup.- semiconductor layer 4 exceeds the built-in potential between the P base layer 5 and the N.sup.+ emitter layer 6. When this parasitic transistor becomes conductive, the main current can not be controlled by the gate voltage V.sub.GE applied to the gate electrode 10 any more. Accordingly, having the parasitic transistor become conductive will result in breakdown of the UMOS 40. This is common in UMOSs in general.
If the contact area between the P base layer 65 and the emitter electrode 72 decreases excessively, the contact resistance therebetween increases so that the potential of the P base layer 65 is apt to exceed the potential of the N.sup.+ emitter layer 66. That is, the parasitic transistor will become conductive easily. That is, the UMOS-IGBT and the UMOS have a problem that the effect of decreasing the ON voltage V.sub.CE(sat) can not be expected and the breakdown tolerance (which can be estimated with the magnitude of an upper limit of the main current which can be caused to flow while conduction of the parasitic transistor is avoided, for example) decreases if they are excessively miniaturized.
In the UMOS-IGBT 80 which is the second conventional example, to prevent breakdown due to the conduction of the parasitic transistor, the ratio of the contact area with the N.sup.+ emitter layer 66 in the entire contact area of the emitter electrode 72 is controlled to 40% or below. However, this is accompanied with a decrease in the channel region 68 because the N.sup.+ emitter layer 66 is in the stripe form perpendicular to the gate electrode 70 in the UMOS-IGBT 80. As a result, an increase of the ON voltage V.sub.CE(sat) is caused. That is, in the conventional devices, only adjusting the ratios of the contact areas with the emitter electrode 72 between the N.sup.+ emitter layer 66 and the P base layer 65 will not consistently realize the decrease in the ON voltage V.sub.CE(sat) and the enhancement of the breakdown tolerance.
Furthermore, with the UMOS-IGBT 80 as an example, quantitative evaluation on the breakdown tolerance shows the result of only 12 A/cm.sup.2. This means that it is not sufficient to prevent breakdown due to conduction of the parasitic transistor to control the ratio of the contact area with the N.sup.+ emitter layer 66 in the entire contact area of the emitter electrode 72 to 40% or below. The procedure of this evaluation is shown below.
FIG. 43 shows a plan view of the UMOS-IGBT 80. FIG. 43 shows the upper main surface of the UMOS-IGBT 80 with the emitter electrode 72 removed therefrom, that is, the upper main surface of the semiconductor base body 60. As shown in FIG. 43, the unit cell width Wcel, the interval of the gate electrode 70, i.e., the trench interval Wt, the stripe width Wn of the N.sup.+ emitter layer 66 and the stripe width Wp of the P base layer 65 are defined, respectively. Furthermore, the maximum distance Lmax is defined as the distance from the exposure surface of the P base layer 65 to the farthest one of the points on an intersection of the boundary of the N.sup.+ emitter layer 66 and the P base layer 65 and the trench 67. This maximum distance Lmax is one factor which defines the lateral resistance in the P base layer 65 right under the N.sup.+ emitter layer 66. In the UMOS-IGBT 80, the maximum distance Lmax corresponds to a half of the stripe width Wn.
Also, the electric resistance Rpn of the P base layer 65 along the path defining the maximum distance Lmax is defined. The electric resistance Rpn corresponds to one which is obtained by integrating the resistivity .rho. in the depth direction of the P base layer 65 in the depth direction D, the width direction W (FIG. 43) and further integrating it from zero to the maximum distance Lmax along the length direction L (FIG. 43). That is, the electric resistance R.sub.0 pn is given by the expression 1. EQU R.sub.0 pn=.intg.dL{.intg.dD.multidot..rho.(L,D,W)} (1)
If the electric resistance and the resistivity per unit width along the width direction W is represented by Rpn, .rho.(L,D), respectively, then the electric resistance Rpn is given by the expression 2. EQU R.sub.0 pn=.intg.dL{.intg.dD.multidot..rho.(L,D)} (2)
Furthermore, if the integration value in the depth D direction of the resistivity .rho.(L,D) is represented by the resistivity .rho..sub.pn, then the electric resistance Rpn is given by the expression 3. EQU Rpn=.intg.dL.multidot..rho..sub.pn (3)
Accordingly, the electric resistance Rpn is given by the expression 4. EQU Rpn=Lmax.multidot..rho..sub.pn (4)
The hole current density Jp in the P base layer 65 right under the N.sup.+ emitter layer 66 causes a voltage determined by the resistivity .rho..sub.pn and the maximum distance Lmax at the junction portion of the P base layer 65 and the N.sup.+ emitter layer 66. If this voltage exceeds the built-in potential Vpn peculiar to this junction portion, the parasitic transistor becomes conductive. Therefore, the current density Jp must satisfy the condition given by the expression 5 to avoid conduction of the parasitic transistor. EQU Vpn&gt;Jp.multidot..rho..sub.pn.multidot.Lmax (5)
The resistivity .rho..sub.pn defines the gate threshold voltage V.sub.GE(th), therefore it is set to an almost constant value in semiconductor elements for electric power. The gate threshold voltage V.sub.GE(th) is usually set in the range of 1V to 5V, so that the impurity concentration in the P base layer 65 is about 1.times.10.sup.16 to 1.times.10.sup.17 cm.sup.-3. In this range of concentration, the resistivity .rho..sub.pn is in inverse proportion to the impurity concentration in the range of 50 .OMEGA.cm to 0.5 .OMEGA.cm.
If the gate threshold voltage V.sub.GE(th) is selected to 4 V which is a typical value, the value of the resistivity .rho..sub.pn is given by the expression 6. EQU .rho..sub.pn.perspectiveto.25 k.OMEGA..mu.m=2.5 .OMEGA.cm (6)
In the UMOS-IGBT 80, as described above, the ratio of the contact area with the N.sup.+ emitter layer 66 in the entire contact area of the emitter electrode 72 is controlled to 40% or below. This corresponds to that the ratio of stripe width Wn and the stripe width Wp is given by the expression 7. ##EQU1##
As typical and adequate values, 12 .mu.m is given as the stripe width Wn, 18 .mu.m is given as the stripe width Wp, and 3 .mu.m is given as the trench interval Wt, respectively, and typically 0.6 V is given as the built-in potential Vpn, then the magnitude of the current density Jp which can be passed without having the parasitic transistor conductive is given by the expression 8. ##EQU2##
The current given by the current density Jp flows through the unit cell. The ratio of the hole current flowing in the P base layer 65 in the main current (collector current) flowing through the device is about 0.3. Accordingly, the magnitude J of the main current which can be caused to flow without allowing the parasitic transistor to be conductive is given by the expression 9. ##EQU3##
That is to say, in the UMOS-IGBT 80, the magnitude of the main current which can be passed while preventing conduction of the parasitic transistor is only 12 A/cm.sup.2. As the rated current of IGBT for large electric power is 50 through 200 A/cm.sup.2, this UMOS-IGBT 80 can not be used for the large electric power with its structure as it is.
The UMOS-IGBT 80 also has a problem that formation of the trench 67 in the semiconductor base body 60 causes internal defects of the semiconductor base body 60. This is the same in the UMOS 40, too. FIG. 44 shows such a defect. FIG. 44 is a front section view of the UMOS 40, where the defect is shown on the basis of an image obtained by using a scanning electron microscope (SEM). Similar defects are observed in the UMOS-IGBT 80, too. As shown in FIG. 44, the defect 15 is observed in the part of the semiconductor base body 20 interposed between the trenches 7. This defect 15 extends along a plane inclined by 45.degree. from the upper main surface of the semiconductor base body 20 starting from the opening portion of the trenches 7. That is, it is considered that the defect 15 occurs along the &lt;111&gt; plane of the semiconductor base body 20. It is also considered that a defect is not caused from the bottom portion of the trench 7 because the bottom portion has a relatively round shape.
This defect 15 does not cause problems in practical use in the UMOS, but it causes an increase in the ON voltage V.sub.CE(sat) in the UMOS-IGBT. That is, if the defect 15 reaches the N.sup.- semiconductor layer 64, the N.sup.- semiconductor layer 64 deteriorates. In the UMOS-IGBT, as the bipolar transistor plays an important role, advance of the deterioration of the N.sup.- semiconductor layer 64 will increase the ON voltage V.sub.CE(sat). That is, in the conventional UMOS-IGBT, it has been a problem that the decrease of the ON voltage V.sub.CE(sat) is hindered also by the defects caused due to the trench 67.
Further, in the UMOS, the UMOS-IGBT for electric power, to prevent excessive increase of temperature or to control overcurrent, a sense region for sensing them is often provided on the upper main surface of the semiconductor base body 60. FIG. 45 is a plan view showing the vicinity of the sense region in the UMOS-IGBT 80. FIG. 45 shows the upper main surface of the UMOS-IGBT 80 with the emitter electrode 72 removed therefrom, that is, the upper main surface of the semiconductor base body 60. As shown in FIG. 45, a sense pad 79 and a sense region 78 are formed on the upper main surface of the semiconductor base body 60 in addition to a cell region 77 in which unit cells 76 are arranged. The sense region 78 is formed of a line of unit cell. Accordingly, miniaturization of unit cells will cause signal detectable in the sense region 78 to be so small that the sensing function can not be effected sufficiently. That is, it has been a problem that it is difficult to decrease the ON voltage V.sub.CE(sat) maintaining the sensing function.
Furthermore, in the UMOS 40 and the UMOS-IGBT 80, even if the decrease in the ON voltage V.sub.CE(sat) of the element itself is realized by miniaturizing unit cells, there remains a problem that it does not contribute sufficiently to the decrease in the ON voltage V.sub.CE(sat) for the entire device due to the voltage drop occurring in the wire electrically connecting the emitter electrode 72 and the like and the external electrode to serve as a path of the main current.
Also, in the UMOS 40, as the trench is formed in the lattice-like form, portions where it intersects in the "+" form exist in the trenches 7. There has been a problem that it is difficult to bury the gate electrode 10 at these "+"-shaped intersections. In a device having the trench 7 formed in the stripe form such as the UMOS-IGBT 80 also has portions where it intersects in the "T" shape or "L" shape at end portions of the stripes. At these T-shaped or L-shaped intersections, it is also difficult to bury the gate electrode 70. That is, the conventional UMOS and UMOS-IGBT had a problem that it is not easy to bury the gate electrodes 10, 70. This problem becomes more serious as the unit cells are miniaturized more.
As described above, the conventional UMOS and UMOS-IGBT have involved the problem that there exist factors for hindering a decrease in the ON voltage (ON resistance), and that it is difficult to increase the breakdown tolerance. Furthermore, they have involved the problem that it becomes more difficult to bury the gate electrodes in trenches as the unit cells are miniaturized more.